English
The basics of setting up hardware verification testbenches using OVM configuration classes
By Arjun Mohan and Ashish Kumar, Mentor Graphics
Embedded.com (04/05/10, 01:36:00 PM EDT)
The Open Verification Methodology (OVM) has been available for download under the Apache 2.0 license since January 2008. Signs of an ecosystem have gradually emerged since then. As just one example, consider the OVM Forum.
As of this writing in early 2010, the forum has more than 1,300 topic threads containing more than 5,200 posts, which almost certainly makes it the most vibrant Web destination devoted to test-bench reuse topics.
However, from perusing the forum and speaking with colleagues working on verification of IC designs, it's clear that to date OVM has been used more to tinker with than to transform the building, use and maintenance of test-benches.
Verification engineers are still using events in their scoreboards to communicate with the monitor, still writing jumbo drivers with hundreds of interface instances and still propagating these interfaces using successive assign_vi tasks or arguments in the constructor.
For the uninitiated, all these are signs of poorly optimized architecture—and of the yet-to-be-realized promise of OVM.
A major part of this promise is that OVM components can be configured into various flavors via configuration classes, which is the subject of this article.
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