Integrating analog video interface IP into SoCs delivers superb image quality (Part II)
By Manuel Mota, João Risques, Synopsys, Inc.
edadesignline.com (April 29, 2010)
Analog video interfaces are essential components of digital home and personal entertainment systems. This is mainly due to their ability to deliver very high image quality with very low power consumption while maintaining compatibility with most modern and earlier-generation video devices where analog video interfaces predominate. In the past, analog video interfaces were implemented using external components. With the proliferation of richer multimedia content in advanced consumer electronics such as DVD players, digital TVs and set-top boxes, integrating high-speed analog interface intellectual property (IP) — including analog video interfaces and other multimedia analog and digital interfaces — into systems-on-chip (SoCs) has become critical to achieve the necessary processing power and image quality.
Video formats can be divided into the following resolution categories: standard TV (PAL, NTSC, etc.), HDTV (e.g., 1080p) and widescreen VGA formats (e.g., 1920x1200) for PC graphics. All of these formats require the accurate transmission of color, brightness and synchronism information over a long cable. To accomplish this, the video transmitter must be able to transmit the video signal reliably and independent of the quality of the transmission cable. Conversely, the receiver must be able to accurately receive the signal and decode the synchronism information in order to re-create a high-quality image.
Maintaining competitiveness in today's consumer electronic products market requires integrating increased functionality into the same digital SoC, which, in turn, poses key design challenges in terms of power dissipation, form-factor reduction and ability to handle multiple video sources.
E-mail This Article | Printer-Friendly Page |
|
Synopsys, Inc. Hot IP
Related Articles
- Integrating analog video interface IP into SoCs delivers superb image quality (Part I)
- Delivering High Quality Analog Video Signals With Optimized Video DACs
- Defining standard Debug Interface Socket requirements for OCP-compliant multicore SoCs: Part 2
- Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)