Algorithmic delay and synchronization in MPEG audio codecs
By Ranjani H G and Ameet Kalagi, Ittiam Systems Pvt Ltd
Audio DesignLine (05/05/10, 02:26:00 PM EDT)
Introduction
A variety of audio compression technologies are being used today, each having a distinct advantage over the other in terms of compression ratio, coding delay, coding complexity or legacy system compatibility. This makes subset of audio codecs suited for particular systems and makes working with multiple audio compression technologies indispensable.
In designing time-critical systems like conferencing, broadcast transcoding systems or be it in designing any audio and video play-out system, the knowledge of the delay encountered while audio encoding or decoding becomes critical.
Figure 1: Audio Delay encountered in systems
Figure 1 tries to capture the various stages at which audio data encounters delay in different applications and systems.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- Paving the way for the next generation audio codec for TRUE Wireless Stereo (TWS) applications - PART 4 : Achieving the ultimate audio experience
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - Optimizing latency key factor
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
- Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)