English
ARM's v6 balances power, efficiency
 |
ARM's v6 balances power, efficiency
By Crista Souza, EBN
October 19, 2001 (11:36 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011019S0070
With power/performance considerations taking center stage at last week's Microprocessor Forum here, ARM Ltd. shed more light on its upcoming v6 architecture, which is designed to give embedded system OEMs a big boost in megahertz without compromising power efficiency. While specific speed and power consumption levels won't be disclosed until the first v6-based implementation-a soft core-debuts in mid-2002, ARM outlined a number of features added to enhance future embedded products. "Power/performance has always been the ARM story," said John Rayfield, director of research and development at the Cambridge, England, company. "The interesting thing is the high-performance computing people are now hitting the same problems we've had in the embedded space for years." As the complexity of embedded systems grows, it's becoming more important to achieve high performance and low power simultaneously, he said. "We're trying to pragmatically do the right thing to get the best efficiency possible," Rayfield said. Among the features to increase efficiency, the company has added ARM and Thumb instructions to support mixed-endian states, both for little-endian interfaces such as PCI and USB, and big-endian data payloads like TCP/IP and MPEG. "In the new connected world, you have to be a little of both," he said. By implementing the instructions in hardware instead of software, ARM claims to achieve better code density and power efficiency. For multiprocessor designs, a shared- memory attribute was added to improve communication between processors while using fewer megahertz. The shared-memory feature supports multiple ARM designs, as well as designs that use an ARM in combination with DSPs or other embedded processors. Intel Corp. and Texas Instruments Inc. in July licensed the v6 architecture to take advantage of this feature in designing their next-generation processors, Rayfield said. Additionally, a new cache architecture, called V irtual Memory System Architecture, improves performance 20% to 30% by eliminating forced cache flushing by the operating system, according to Rayfield. OR
Related Articles
- Today's DSP Design Challenge - Power Efficiency
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- High Speed, Low Power and Flexibility Drive DisplayPort's Increasing Popularity
- Low Power Design in SoC Using Arm IP
- SamurAI: a 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to- Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow
|
E-mail This Article | 
|
|
Printer-Friendly Page |