DSP cores take comms focus

DSP cores take comms focus
By Patrick Mannion, EE Times
January 4, 2002 (12:15 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011015S0047

MANHASSET, N.Y. — Five of the latest digital signal processing architectures will be scrutinized at the annual Microprocessor Forum this week in San Jose, Calif.

Siroyan Ltd. and Silicon Spice will finally open the doors to their revolutionary architectures, while 3DSP Corp. and LSI Logic Corp. will unveil the latest, high-performance versions of their well-established cores. Adding diversity, Equator Technologies Inc. will launch the latest in its line of high-end DSPs for video/image processing.

With a strong overall focus on communications, the five add to a slew of DSP cores announced over the last 18 months, many of them conceived in a time of readily available venture-capital funding in response to what was a rapidly growing market.

Underscoring how that growth has cooled, figures from analyst firm Forward Concepts (Tempe, Ariz.) show that total worldwide DSP IC shipments will fall from roughly $17 billion in 2000 to about $13 billion in 2001. However, Will Strauss, president of Forward Concepts, said the market is expected to return to strong growth in 2002 at $18 billion, rising at a compound annual growth rate of 19.1 percent to $40 billion or more by 2005.

Room for upstarts

While that market demand has cooled for now, a multitude of applications remain, leading analysts to conclude that there is more than enough room for DSP-core upstarts — such as Adelante, Bops, Improv, nBand and Systemonic — in the face of well-established incumbents like Texas Instruments, Analog Devices, Motorola, Lucent and StarCore.

"To meet the specific performance parameters of the various applications, the industry needs more than a handful of architectures," said Jeff Bier, general manager of Berkeley Design Technology Inc. (Berkeley, Calif.) and leader of a DSP session at the forum on Thursday (Oct. 18). "The multitude of new cores does mesh well w ith an industry move away from packaged processors to ASICs, ASSPs and systems-on-chip."

Of the five companies "going under the knife" this week, Bier pointed to LSI Logic as having the advantage in terms of its breadth of offerings, starting as a core supplier. "They're discussing their core, but they're also licensing that core to other companies, while using it in ASSPs and offering it to ASIC customers for use in custom devices," he said.

ZSP400 wins

At the forum, LSI Logic will unveil its second-generation (G2) architecture, built upon its successful superscalar ZSP400, which to date has design wins with Brecis, Conexant, IBM, Virata (now being bought by GlobeSpan) and Broadcom.

A quad-MAC (multiply-accumulate) core, the G2 ZSP600 adds three more stages to the ZSP400's five-stage pipeline. The six-issue, superscalar device performs 16 x 16 MACs per cycle, has four arithmetic logic units, dual 64-bit data interfaces, an eight-instruction /cycle prefetch and 24-bit addressing.

Manufactured in a 0.13-micron process, the 300-MHz design (vs. ZSP400's 160-MHz at 0.18-micron) gives a total raw performance of 1,200 million MACs and performs 1.8 billion instructions per second. Targeting everything from 3G basestations to mobile handsets to home gateways, the core will have support for soft intellectual property and software design kits by the first quarter of 2002, with evaluation boards available by the second quarter.

For its part, 3DSP (Irvine, Calif.) will unveil the next stage in its core evolution from its SP-5 architecture. LSI Logic and 3DSP are "in a similar space in terms of performance, and both are emphasizing communications applications," said Bier. "Both are also following similar road maps in terms of a second-generation, high-performance variant of previously introduced architectures."

While that may be true in the sense that 3DSP's UniPHY is based on the company's superscalar single- instruction, multiple-data architecture, 3DSP is taking a much more focused route by specifically targeting physical-layer signal processing for broadband communications.

To target those applications, which include baseband processing for wireless 802.11a/.11b as well as wireline xDSL, the UniPHY first takes 3DSP's basic SP-5, two-way, superscalar, five-stage pipelined architecture with its SP-x instruction set. To that, 3DSP has added four more stages to the pipeline, incorporated a 64-bit expansion instruction set to allow all the execution units to operate simultaneously and added a novel data path register to avoid data-register bottlenecks resulting from the highly parallel processing.

In a 0.13-micron process, at 1.8 volts, the 400-MHz core performs 16 gigaoperations/s and can do a 256-point complex fast Fourier transform in 659 cycles. The core will be available for licensing at the end of the fourth quarter.

After almost a year in production, Silicon Spice will fully disclose its much-touted SpiceEngine architecture, which is currently selling into the voice-over-packet market under the Calisto name.

Announced last year, before Silicon Spice was bought by Broadcom Corp., "the SE is a reasonably general-purpose DSP," said John Nickolls, director of architecture for Broadcom's carrier access business unit and one of the designers of the SE. The Calisto chip (BCM1500) comprises a control RISC processor and 16 SE vector processors. "Voice-over-packet is fundamentally a multichannel problem, so we knew we wanted to leverage the channel parallelism as much as possible," said Nickolls. "It's a relatively simple DSP, but it's intended not to pull a lot of resources out of a system so you can put a lot of copies on a chip."

Memory break, power break

At the forum, Nickolls will describe how the SE's use of vector registers speeds the processing of vectors and arrays of data, "which is what you encounter in most signal-pro cessing applications," he said. The typical DSP uses a multiport-memory approach to do MACs on operands obtained from memory. "When you put 16 of those on a chip, you have either a lot of memory or a huge demand on the memory that's there," said Nickolls. "That's very difficult to support, so we decided to build a large register file and organize it like a vector register file — like the old Cray [supercomputer] from the mid-'70s. They also used vector register files to avoid [going] into memory for every operand."

The advantage, said Nickolls, is reduced power consumption, since the core doesn't have to keep hitting memory every time an operand is needed.

Nickolls will also describe the SE's unusual control structure, which is partially configurable and partially instruction driven. The device is configurable in the sense that it allows very wide instruction-level parallelism (128 bits). But the instructions themselves are only 24 bits.

"This allows us, within the critical loops such as M ACs and other vector signal-processing operations, to get a lot of width to describe parallel operations in these configurable control instructions," said Nickolls. The instructions reside in the configuration register. The compiler then builds the configurable instructions as it needs them.

An important point, in Nickolls' view, is that the SE allows all this DSP work to be done in C, making it a very easy compiler target. Broadcom developed an extensive compiler, for which Nickolls will demo some C-code examples, some loops and what the compiler generates.

While the SE core will be going into other Broadcom chips, there are no plans to license it. "While we're seeing lots of design wins, there's just not too much equipment going out the door," Nickolls said. "My sense is that this [downturn] is driven more by people's sense of the economic times. We know people need this, it's just hard to say if it's going to get pulled hard over the next year or so."

More Microprocessor Forum coverage.