Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP
Using unified modeling methods to reduce embedded hardware/software development
By Steve Brown, Cadence Design Systems, Inc.
Embedded.com (05/10/10, 08:08:00 PM EDT)
Today’s Internet devices are powered by sophisticated electronic circuits driven by multiple layers of software. These circuits are so complex they are called Systems on Chip (SoC) because they contain all the sub-components of a powerful personal computer. SoC development costs continue to grow rapidly, driven by increasing demand for more functionality, device mobility, and improved usability. These new capabilities demand more sophisticated software executing on multicore hardware and other special purpose accelerators to meet power and performance requirements. SoC development team productivity cannot keep up with the growth in complexity. The costs of developing the most complex SoCs now threaten to exceed $100M, requiring sales of tens of millions of units to return a profit on that investment
E-mail This Article | Printer-Friendly Page |
|
Cadence Hot IP
Related Articles
- Unified Verification for Hardware and Embedded Software Developers
- Integration drives embedded software development and hardware debug
- Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development
- Managing the complexity of embedded software development through design automation tools
- Embedded software development tools - a third way
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology