DSPs duel FPGAs for 3G baseband processing chores

DSPs duel FPGAs for 3G baseband processing chores
By Chris Edwardsand Patrick Mannion, EE Times
October 9, 2001 (1:25 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011008S0051

SAN JOSE, Calif. — FPGA and DSP vendors are squaring off to pitch their respective technologies as the only means of effectively handling the enormous up-front processing requirements for third-generation (3G) cellular basestations.

FPGA manufacturers such as Altera Corp. are promoting flexibility, speed and room for modification — an advantage as 3G standards take shape. In the meantime, DSP vendors, including Analog Devices Inc. and Texas Instruments Inc., are also promoting flexibility, but at lower cost and with greater tool and software support.

Analog Devices (Norwood, Mass.) this week will roll out its latest ADSP-TS-101S TigerSharc DSP, with added instructions that will make it the first to do both the chip-rate and symbol-rate processing required for 3G basestations.

TI's latest 3G basestation DSP, the C6416, has a coprocessor for symbol-rate processing. A spokeswoman for the StarCore alliance of Agere and Motorola said t hat the company is considering extra chip-rate processing support in its DSPs. "StarCore has been evaluating the trade-offs of adding specific support for turbo coding and chip-rate processing in future versions," she said, but added that the group has not announced details of its findings.

ADI is also announcing a suite of libraries for Layer 1 functions that will allow the TigerSharc to support all 3G standards: wideband-CDMA, for Europe and Japan markets; cdma2000 in the United States and South Korea; and time-division, synchronous CDMA, the 3G choice in China.

The high processing requirements of 3G systems result partly from the 2-Mbit/second data rates, as per the UMTS W-CDMA standard. More important, however, is the CDMA coding technique, which requires high-speed, chip-rate processing to perform the pseudorandom-number generation, channel spreading, mux/demux, rake receiver and symbol-combining functions.

Speaking at last week's Communications Design Conference here, Asif Batada, manager of wireless marketing strategy at Altera, put the processing requirements in perspective.

"To date, phones based on GSM or IS-136 [the North American TDMA standard] have required 100 and 200 Mips of processing power [respectively]," Batada said. "As we move to 3G and also start to incorporate advanced features such as multiuser detection, that jumps to 5,000 Mips — a 50x jump. There's no way a general-purpose DSP can handle that sort of chip-rate processing for multiple channels."

Advanced features

Other advanced features that Batada predicts will be needed include adaptive antennas, in the form of either beam forming or antenna diversity. Such sophisticated features will become an intrinsic part of basestation design by 2005, said analyst Will Strauss, president of Forward Concepts (Tempe, Ariz.).

In the meantime, Batada used the conference to demonstrate a multiuser-detection (MUD) implementation based on FPGAs. MUD eliminates the channel noise from other users in the band (all CDMA users are on the same frequency, separated by a spreading code) through cancellation techniques. Using eight antennas, Batada showed how the Altera solution achieved a 50 percent increase in gain.

"The use of FPGAs allows the bulk of the processing to be done in the digital domain," not the analog, he said, citing the analog section as one of the most expensive parts of a basestation.

In a separate demonstration that used beam forming, Batada showed that the combination of a 3.84-MHz chip rate, eight antennas and 6-bit sample data could support up to 32 users. The processing required 963 million multiply-accumulates (MACs) per second.

However, 32 users per basestation and 963 MACs don't impress Ron Levy, director of marketing and business development at Lenslet Labs (Ramat-Gan, Israel). "If carriers are to recoup their investment in spectrum licenses, they're going to need to support users in the hundreds per basestation — and neither conventional FPGAs nor DSPs are going to get them there," he said.

Levy was in San Jose to announce Lenslet's Optical Digital Signal Processing Engines. The engines, said Levy, can take processing from gigaoperations per second today to teraoperations/s by 2005.

In the meantime, as Lenslet gets its technology to market, basestation designers are left to choose from conventional technologies, initially high in cost and relatively low in capacity. Andrew McCann, wireless-infrastructure marketing manager for Analog Devices, said that first-generation 3G basestations were designed to get to market fast and have not been cost-optimized.

"Nobody wanted to be in the position when the operator called that they didn't have [a 3G basestation offering]," said McCann. Typically, he said, "high-end FPGAs are used in the chip-rate section, with lots of external memory because they do not have much [memory] on-chip. And the DSP is used for symbol-rate processing."

McCann contended that costs ca n be saved by designing out the FPGAs in the front end and expanding the role of the programmable DSP to cover the chip-rate processing — exactly the job the ADSP-TS-101S TigerSharc DSP is designed to tackle.

"Putting a hard partition between the chip-rate and symbol-rate processing sections leads to an inefficient use of resources," said McCann.

Lenslet's Levy agreed, but took the proposition a step further. "Our goal is to get rid of both DSPs and FPGAs, as well as all the other multiple sourcing a basestation manufacturer must do as they incorporate MUD and adaptive antennas, bringing it all down to algorithms that can be run on our Optical Digital Signal Processing Engines," Levy said.

Until that happens, however, 3G systems still face the problem of handling a mixture of voice and data traffic. The two types of traffic call for different levels of processing in the two sections. With voice calls, the more users there are, the more processing is needed to despread the bits from each of the received channels. In contrast, higher-bandwidth data channels tend to need a lot less chip-rate processing.

Voice channels call for less processing in the symbol-rate section than data. That's because the "turbo" decoding stage takes more processing power than the Viterbi processing used for voice channels.

ADI's solution is to use clusters of the new TigerSharc DSPs so that chip-rate and symbol-rate processing can be traded off against each other.

Workload issues

The problem for a DSP in the chip-rate section is the workload involved. "Millions of complex MACs need to be performed," said ADI's McCann. "But the complex MAC needed is a correlation of radio data with a code sequence. The code sequence is always made up of --1 and +1 values."

The TigerSharc designers have taken that information and created a new instruction that performs 16 correlations in parallel, he said. "This brings in the possibility of doing chip-rate processing," said McCann.

In the symbol rate, the biggest overhead for a programmable DSP comes from the Viterbi and turbo decoders. ADI has chosen to implement instructions that handle the basic primitives needed for those algorithms. The operations that ADI focused on for the turbo primitives are add, compare and select functions.

Meanwhile, the StarCore DSP architecture, developed jointly by Agere Systems and Motorola Semiconductor, implements special instructions for Viterbi decoding. In contrast, Texas Instruments, for its C6416 DSP, opted to add dedicated coprocessors to a DSP core.

The spokeswoman for the StarCore group said it is possible to add custom instructions to the SC140 DSP's multiprocessor architecture through instruction-set-level plug-in modules. "A large portion of the chip-rate processing — much greater than half of the function — is already done on the DSP," she said.

The new version of ADI's TigerSharc runs at 180 MHz and is built on a 0.13-micron Taiwan Semiconductor Manufacturing Co. process. Analog Devic es is working on a faster version, converting the existing standard-cell design into one that uses full-custom circuit techniques to take the clock speed up to 500 MHz by the end of 2002.

"Our plan is to go very aggressive on circuit design and layout," said McCann. "We might change the pipeline by slipping in an extra memory-fetch stage but that will be transparent to the programmer. We are looking at some in-between approaches. We have a 1-volt supply on this device. We are considering higher voltages to achieve higher speeds."

Chris Edwards is the editor of Electronics Times, EE Times' sister publication in the United Kingdom.

Copyright © 2003 CMP Media, LLC | Privacy Statement