English
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Current thoughts on custom IC design
By Jim Hogan
edadesignline.com (May 18, 2010)
After 35 plus years of being in the semiconductor business, custom IC design still is an extremely interesting challenge.
I have always felt the job of a designer is to optimize designs within the process capabilities. The design exercise is still a process of trading off the marketing requirements of function, performance, cost and power. This is especially true in the case of custom design. There is never a perfect answer, only a most right, or said differently, the least wrong. This is fundamentally due to the inherent reliance of statistical process control in discrete manufacturing, such as semiconductor, chemical, genetics, and steel foundries.
Designers relying on discreet manufacturing processes need to rely on accurate process models (SPICE for semiconductor). As variance increases, more models or corners are required to represent the process capability.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™