Custom cores limit SoC turnaround

Custom cores limit SoC turnaround
By Coby Zelnik, Senior Vice President, Business Development, Sagantec, Fremont, Calif., , EE Times
October 4, 2001 (4:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011004S0110

System-on chip implementation relies on a designer's ability to combine cell-based logic with specialized full-custom blocks for embedded processors, memories and analog functions. Consequently, ready availability of full-custom blocks plays a significant role in determining the speed of the SoC design process and time to working silicon. Unfortunately, intellectual-property (IP) blocks often need to be reimplemented, migrated or optimized to support new process technologies, different foundries or specific requirements for timing, area or power. Yet conventional approaches rely on manual layout-conversion methods that require months of effort by specialists. As a result, SoC design often stalls waiting for key blocks to become available.

Newer tools automate full-custom reimplementation and optimization, opening new opportunities for IP vendors and SoC development organizations. Using this automated method, engineering teams are able to focus squa rely on design objectives, handle reimplementation more efficiently and rapidly produce higher-quality multiblock SoC designs.

In building systems-on-chip, engineering teams use multiple types of components from diverse sources. Along with cell-based logic blocks from internal design efforts, an SoC design will typically need to mix full-custom logic blocks, such as hard-IP cores for embedded processors from major IP vendors, compiled memory blocks from specialty IP vendors, with unique analog and mixed-signal elements from both in-house and third-party analog specialists. In each case, the IP core vendor or developer will attempt to deliver cores targeted for as large a number of leading foundry processes as possible.

Increasingly, however, SoC design organizations need memory, processor or analog/mixed-signal cores that are available in a special process even beyond those supported by the core provider. In addition, even when the core is available for the SoC's target process, design engineers fi nd that the third-party cores require further optimization for timing, speed, area or power to meet their overall requirements for high-volume applications.

For engineering teams, the availability of optimized cores for their target process technology is of course paramount. The unavailability of a silicon-ready core for any function introduces significant delays in the entire SoC silicon release schedule. Worse, engineering teams face few good choices for filling in the needed function: The team would need to select an alternative that is available in their target process, negotiate with the IP provider for reimplementation in the target technology or take on the additional task itself. None of these alternatives is desirable.

Unfortunately, the gap between design requirements and IP silicon availability is likely to grow. Modern cores are highly optimized designs that require intensive effort by IP vendors just to support a limited number of processes and foundries. Retargeting the full-custom pr ocessor, memory or analog/mixed-signal blocks commonly used in today's SoC designs has traditionally been a slow, complex task that requires careful, methodical manual work by layout engineers.

In the traditional approach, a layout engineer may need to manipulate the geometry, location and orientation of every device in the design with little more help than basic CAD tools. Iterating between CAD tools and transistor-level simulation tools, an engineering team will verify design performance, area and power — and return to manual CAD-based manipulation to resize design features to correct any problems. This sort of traditional manual process typically requires months of effort to work through a complex design and produce a verified, design-rule-correct result. For highly specialized designs such as memory and analog/mixed-signal, unique design requirements demand availability of sufficiently experienced and skilled engineering resources. In particular, analog/mixed-signal designs typically require sc arce specialists able to work comfortably in both the circuit and physical design levels simultaneously, because function and physical structure are so highly interdependent in these types of circuits.

In this environment, no company can expect to use traditional manual methods to meet a rising tide of requests for reimplementation and optimization. With conventional manual approaches, both commercial IP houses and in-house design-reuse specialists can expect to find themselves laboring under a growing backlog of requests to retarget and optimize designs of key IP blocks. For engineering organizations, this growing backlog will ripple through SoC design efforts, resulting in increased delays and missed delivery dates for critical design projects. Recently, new physical design approaches are now able to break this logjam by automating the most critical aspects of physical design re-implementation and optimization.

For any design, the first implementation of a physical layout is an extremely time-con suming process. Engineers must engage in detailed design trade-offs, experimentation and simulation to achieve a working physical architecture. Unfortunately, with traditional methods, the amount of effort needed to target a different process is nearly the same as that involved in completing the first implementation. Similarly, a reimplementation effort requires engineers to pay close attention to every detail in a physical design to ensure that every edge of every polygon is correctly placed.

In newer approaches, automation of this full-custom physical-design process relies on technology that is able to leverage previous design results, fully exploiting the information available in existing physical-design architectures. With these automated methods, layout engineers reuse an existing physical design to create a new layout targeted for a different process technology or optimized for specific performance parameters. The latest physical-design reimplementation and optimization tools, such as Sagantec's S iClone, scan an existing layout, reading existing GDSII or native data from leading EDA environments. During this scan, this type of tool is capable of automatically recognizing all devices such as MOS transistors, resistors and capacitors, while it identifies symmetry or matching within the original layout — preserving those qualities in the migrated layout. The technology sizes all existing devices to the designer's requirements and can even apply different shrink rates or design rules depending on the specific portion of the circuit. Rather than forcing layout engineers to engage in slow manual tasks, this approach performs rapid reimplementation by carefully repositioning all layout elements and polygon edges so that the generated layout is design-rule correct and optimized for its design performance targets.

This approach applies not only to reimplementation of existing designs in new processes but also to optimization of an existing design to improve its timing, speed, area or power for an ex isting process. With this approach, design engineers can typically gain a 20 to 25 percent improvement in density without any specialized attention to optimization. With today's sub-150-nanometer process technologies, however, detailed layout optimization has become essential for dealing with increased electrical and physical effects such as signal integrity, electromigration and process quality-related issues. Now, designers can tune designs for specific power and timing targets by specifying required transistor sizes. Typically, engineers use existing design tools to determine critical paths and determine target transistor sizes that need adjustment to meet designer-specified delay and power targets. In turn, the optimization tools are able to use these results to change the target transistors needed to meet the optimization objectives.

At the heart of this approach, layout compaction technology works like a design-rule checker tool capable of not only analyzing an existing physical layout, but also c onstructing all rule distances to the minimum specified in the design rules, ensuring maximum design density.

To work with existing design flows in the practical application of reimplementation and optimization techniques, new tools need to preserve the hierarchy of an existing design. Engineering teams fully expect to be able to correlate schematic and netlist design representations with physical-design representations. Any physical transformation that flattens an existing hierarchical representation — or varies it in any significant way — would be an obstacle for any further attempt to make and verify corrections or support an effective design-reuse policy. By maintaining a consistent structure for a design across its schematic and netlist representations, this new approach lets engineers work with new, migrated layouts with existing design and verification tools.

Layout engineers can best use this type of technology in concert with their existing design and verification tools. In a mig ration project, they use an iterative flow that is similar to existing methods: The design engineer extracts the results and verifies them against timing, area and power objectives. Unlike earlier methods, however, the engineer relies on the resizing technology to automatically adjust specific devices to meet those objectives. Because this automated approach avoids the tedious manual efforts of traditional methods, layout engineers find they can complete reimplementation or optimization projects five to 10 times faster than with traditional manual approaches. In turn, they can reliably deliver their full-custom, design-rule-correct blocks to the SoC design team — relieving increasing pressure for availability of full-custom blocks needed to meet tight SoC development schedules.

SoC design methodology is intended to improve productivity and shorten design cycle time by reusing already developed and qualified circuit components like CPU, memory and mixed-signal functions. This methodology relies on t he ready availability of these components implemented and optimized for a fabrication technology and the specific application. To meet product introduction deadlines, the traditional reimplementation methods have proven to be impractical and so new solutions are required. Physical-design-reuse techniques with tools such as SiClone have proven to automate and accelerate reimplementation tasks by an order of magnitude. This opens the component-availability bottleneck and enables rapid implementation and introduction of new, integrated products utilizing latest fabrication technologies.