IP Forum highlights challenges to inward investment
![]() |
IP Forum highlights challenges to inward investment
By Nick Flaherty, EE Times UK
October 1, 2001 (7:52 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010917S0018
Intellectual property rights (IPR) are one of the major challenges in encouraging more inward investment and international collaboration in science and technology, says the UK's science minister, Lord Sainsbury. He was speaking at the first high-technology forum between the UK and South Korea held in this country. He highlighted IPR and access to information as two of the main issues that were holding back collaboration. "Confidence in the security of one's IPR is essential to any such relationship, and so both British and Korean organisations need to be clear about ownership and procedures for handling disagreements," he said. "The loss of confidence is likely to do considerable damage to UK/Korea relations in this area of collaboration if we are not careful." This forum, the second overall, was held in Bristol and saw around 40 representatives of Korean companies talking with UK companies such as BAE Systems and Marconi on topics including nano-technology, photonics, bio-technology and environmental technology. The Korean delegation included representatives from LG and Samsung, as well as government research institutes. It also included Ryu Chang-Moo, deputy minister for the Korean ministry of commerce, industry and energy.
Related Articles
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Key considerations and challenges when choosing LDOs
- Reliability challenges in 3D IC semiconductor design
- Handling the Challenges of Building HPC Systems We Need
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |