Soc Design -> Emulation verifies multiple network interfaces
![]() |
Lightweight Bluetooth headset has improved power
By Darren Rea, EE Times UK
September 13, 2001 (12:03 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010913S0050
Ericsson has unveiled its latest Bluetooth headset It says the main benefit of the HBH-15 headset over the original model is an improved battery design that allows a talk time of around five hours and a standby time of approximately 110 hours. The headset weighs 32g and offers voice dialling support and single-button interface. It is expected to go on sale during Q4.
Related Articles
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
- A versatile Control Network of power domains in a low power SoC
- Implement a VXLAN-based network into an SoC
- Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SoC
- Using simulation and emulation together to create complex SoCs
New Articles
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
Most Popular
- System Verilog Assertions Simplified
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
- Synthesis Methodology & Netlist Qualification
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |