English
CompactPCI Interconnect Spec To Be Enhanced
 |
CompactPCI Interconnect Spec To Be Enhanced
By Embedded.com
August 3, 2001 (4:36 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010803S0074
Wakefield, MA -- The PCI Industrial Computer Manufacturing Group (PICMG), a consortium of over 700 companies that collaborate to adapt PCI technology for use in industrial and telecommunication computing applications, has held a kick-off meeting for the PICMG 2.17 StarFabric subcommittee, whose purpose is to provide guidelines for implementing the StarFabric interconnect in a CompactPCI environment. The group had its first meeting at the Embedded Systems Conference in Chicago on July 11. StarFabric is a point-to-point switched backplane and chassis-to-chassis interconnect for next-generation communication equipment. The CompactPCI StarFabric interconnect specification will define redundant, switched, high-speed point-to-point connectivity among some or all slots using StarFabric switch cards. The StarFabric interconnect can coexist with 64-bit CompactPCI, H.110., and Ethernet backplanes, as defined in PICMG 2.16. Systems that take advantage of StarFabric features can be designed to utilize existing single board computers (SBCs) and node cards. Special slots for active switching fabric elements, which may be redundant, will also be specified. Todd Comins of StarGen was elected by meeting attendees to chair the PICMG 2.17 subcommittee. Ed Nuber of Agere was elected secretary and Steve Christo,also of StarGen, was selected to be the specification editor. The subcommittee plans to complete the 2.17 specification by the second quarter of 2002. Founded in 1994, PICMG's original mission was to extend the PCI standard beyond the desktop, into industrial and telecommunications applications. PICMG developed the CompactPCI specification and continues to develop extensions and improvements. For information about PICMG membership, or to find out how to obtain PICMG specifications, visit the PICMG website at www,picmg.org .
Related Articles
- A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect
- Network-on-chip (NoC) interconnect topologies explained
- The network-on-chip interconnect is the SoC
- Licensing Interconnect IP for Fun & Profit
- The Gatekeeper of a Successful Design is the Interconnect
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
|
E-mail This Article | 
|
|
Printer-Friendly Page |