IP vendors making leap from source code to silicon
IP vendors making leap from source code to silicon
By Anthony Cataldo, EE Times
May 15, 2001 (3:25 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010515S0048
SANTA CLARA, Calif. No longer content to provide functional building blocks that are subsumed into larger chip designs, intellectual property (IP) vendors are starting to put the pieces together themselves and in some cases are designing full-fledged devices ready for fabrication. The definition of this so-called "domain IP" varies depending on the source, but the end result is the same: larger aggregations of discrete circuits sold as larger functional units. The trend begs the question of when a core provider becomes a fabless semiconductor supplier. Nurlogic Design Inc. (San Diego) is an example of a company that is blurring the lines between those two categories. Nurlogic has spent the past four years building an IP portfolio that includes analog and mixed-signal circuitry, I/Os, standard-cell libraries, memory and bus interfaces. Now, it's moving into what it calls its "next phase" by providing not only IP but application-specific s tandard products (ASSPs), starting with physical-layer devices targeting the communications markets. The company plans to start out by providing fully functional ICs that can be sold to a customer, which can use the part under its own brand. It also plans to provide application-specific products sold under the Nurlogic brand name. In the next few weeks, one of Nurlogic's customers is expected to roll out a silicon germanium-based chip for a vertical-cavity surface-emitting laser. The device was designed by Nurlogic and will be produced by partner IBM Microelectronics. Rather than develop the device itself, the undisclosed customer focused on designing a special package, said Darla Berkel, senior marketing manager for Nurlogic. She called the move to full-fledged devices and ASSPs "a natural step for an IP house. Instead of providing an LVDS and a PLL, a wrapper and some gates, you're now selling it as one entity." The move raises questions over conflicts with existing customers that might be designing similar products. But Berkel said that's not an issue for Nurlogic. "I think we'll have enough of a differentiated product line that there wouldn't be a direct competition situation," she said. Even so, she said the company is just now getting the word out to its customers. Other IP houses are headed down the same path. Zarko Nozica, vice president of applications engineering for IP vendor Leda Systems Inc. (San Jose, Calif.), said the his company is making an effort to provide more domain IP, which he called "large blocks of complex functions for certain applications." Like its competitor Nurlogic, Leda is looking beyond providing discrete circuitry. While it has a wide selection of analog and mixed-signal circuitry the company has some 50 phase-locked loops (PLLs) in its portfolio it's now looking for ways to combine and characterize its various D/A and A/D converters, PLLs and voltage regulators for specific applications, such as Bluetooth, Nozica said. One of the most active areas for the IP trade, whether for individual building blocks or fully functional devices, is chip-to-chip interfaces. IP suppliers have traditionally been a source of delay-locked loops and PLLs, but more often they combine this expertise with emerging interface technologies like HyperTransport, low-voltage differential signaling and Infiniband, among others, according to several IP vendors interviewed. Even the telecom market downturn has not dampened business conditions for IP vendors. The exhibition hall at a recent UMC technology conference here was abuzz with engineers sashaying among different IP vendors' booths, passing business cards and asking pointed questions. "Business is incredible," said Nozica, who found himself constantly torn between greeting customers and answering questions from this reporter. "We're swamped," agreed Nurlogic's Berkel. The privately owned company has been growing more than twofold every year, and expects to do the same this year, she said. John Caruso, president of Analog Integration Partners, also said there's no shortage of customer inquiries. The small Milpitas, Calif.-based company, which designs analog-to-digital interfaces for applications such as LCDs, now employs five engineers and is looking to hire another three or four in the next few months, Caruso said. "My experience with recessions like these is that the first reaction of companies is not to lose money. Then once the situation becomes more clear, they try to drive their products to another level of sophistication," Caruso said. That's a big reason why IP vendors say they are thriving. Another is that their business model has been given the stamp of approval from industry heavyweights. Leda counts Agilent, Conexant, LSI Logic and Ricoh as its customers. And the projects they're being given are nontrivial. Advanced Micro Devices, for example, has tapped Nurlogic for the design of a high-speed PLL for AMD's next-generation microprocessor design, Berkel said. It wasn't al ways easy to get such high-profile projects with top-tier chip companies. In many cases, these chip companies would request the source code so they could tailor the core for their own process technology, only to be rebuffed by IP vendors that wanted to protect themselves in case something went wrong with the design. Companies like Nurlogic still aren't giving out their source code, but Berkel said more integrated device manufacturers are using outside foundries, which is where IP vendors are porting their designs. "We have to meet the standards of third-party foundries, and it's been validated in silicon," Berkel said.
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
E-mail This Article | Printer-Friendly Page |