English
Picking the right built-in self-test strategy for your embedded ASIC
Sunit Bansal and Sumeet Aggarwal
8/2/2010 6:29 PM EDT
Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application. Such test modes usually accompany memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design.
Depending on the implementation of BIST module (Figure 1, below), we may have parallel and serial access capabilities to test the same. This test is performed at wafer level and package level. We usually have multiple packages available for SoC, which has a different number of power pads available.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Picking the right 802.15.4/ZigBee wireless connection for your embedded design
- Is a single-chip SOC processor right for your embedded project?
- Choosing an effective embedded SoC ASIC design strategy
- Choosing the right low power processor for your embedded design
- Select the Right Microcontroller IP for Your High-Integrity SoCs
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology