English
Picking the right built-in self-test strategy for your embedded ASIC
Sunit Bansal and Sumeet Aggarwal
8/2/2010 6:29 PM EDT
Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application. Such test modes usually accompany memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design.
Depending on the implementation of BIST module (Figure 1, below), we may have parallel and serial access capabilities to test the same. This test is performed at wafer level and package level. We usually have multiple packages available for SoC, which has a different number of power pads available.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Picking the right 802.15.4/ZigBee wireless connection for your embedded design
- Is a single-chip SOC processor right for your embedded project?
- Choosing an effective embedded SoC ASIC design strategy
- Choosing the right low power processor for your embedded design
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware