FPGA compilation on-site or in the cloud
Rick Kuhlman, National Instruments
EETimes (8/9/2010 7:10 AM EDT)
It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements. Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- The rise of FPGA technology in High-Performance Computing
- Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA
- FPGA Market Trends with Next-Gen Technology
- eFPGA LUTs Will Outship FPGA LUTs Later This Decade
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)