Novel advances for embedded memory emerge at CICC

Novel advances for embedded memory emerge at CICC
By Rick Merritt, EE Times
May 11, 2001 (2:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010508S0046

SAN DIEGO — Researchers detailed several fresh approaches to smoothing the integration of large amounts of high-performance embedded memory onto the latest ASICs at the Custom Integrated Circuits Conference on Monday (May 7).

NEC Corp. described its progress on a 1-Mbit ferroelectric RAM cell that it expects to embed on a smart card controller that could ship by 2003. The company also revealed a promising non-volatile SRAM architecture still in the labs and based on its ferroelectric work.

Separately, IBM Microelectronics and Mitsubishi Electric Corp. tackled implementation issues arising from the placement of increasing amounts of embedded memory on ASICs. IBM discussed a new method of handling fuses that could simplify the layout of ASICs that use significant chunks of embedded memory. And Mitsubishi showed a new technique aimed at reducing the cost of testing system-on-chip (SoC) devices that use multiple memory cores.

"We're dealing with the problem of lots of embedded memory on an ASIC," said Michael Ouellette, a design engineer for IBM in Essex Junction, Vt. "We've started to see customers come to us wanting 10-to-30 Mbits of SRAM and we think that will continue."

The number of fuses, which are used to provide improved yield for embedded memory cells, threatens to grow to unmanageable proportions, Ouellette said. For example, an ASIC with 64 Mbits of SRAM would require 5,120 fuses, while a 128-Mbit embedded DRAM would need 44,032 fuses. And IBM's next-generation ASIC process will support 256 Mbits of embedded DRAM.

Fuse profusion

To handle the layout problem caused by fuses sprouting on ASICs like crabgrass, IBM has defined a method of gathering them into a compact fuse array in a small corner of an ASIC. The scheme also supports sharing fuses across multiple memory cells and using compression logic to trim down the number of fuses needed for a device. IBM claims the technique could reduce the number of fuses needed for an ASIC with 256 Mbits of embedded DRAM from 88,064 fuses down to 9,216 fuses.

IBM is making the technique available in its 0.11-micron Cu11 ASIC process, which is already in use by some customers. The first prototype ASICs designed in the process should emerge late this year or early next year, Ouellette said.

Separately, Thomas Chadwick, an ASIC development engineer at IBM, detailed a new embedded content addressable memory (CAM) cell created for IBM's SA-27E ASIC library which "should be qualified in a matter of days," Chadwick said.

The device aims to halve the power consumption of an existing CAM and is targeted at communications designs that use CAMs for complex table lookup operations carried out in a single clock cycle. A 512-word x 64-bit test chip was able to hit a search cycle time of 7.5 nanoseconds at V_dd of 1.65 volts.

For its part, Mitsubishi showed how a method of using shared built in self-repair analysis (BISA) could hold down test costs on SoCs that em bed multiple memory cores. In a 100 mm² system-chip made in a 0.13-micron process and featuring five memory cores that take up 10 mm², a designer could save 93 percent of the costs of conventional testing by using shared BISA, said researcher Jun Ohtani. The technique employs a reconfigurable CAM array.

EEPROM replacement

But the highlight of the embedded memory session here was an invited paper from NEC on its work on embedded ferroelectric RAM. Hideo Toyoshima, project manager in the ULSI device development division of NEC in Kanagawa, Japan, showed a 2T/2C FeRAM cell with an 18.7 mm² cell size made in 0.35-micron technology that could replace EEPROM memory in a smart card controller.

The device uses ferroelectric capacitors in a novel cell structure that puts the capacitors at the top of the device where they are fabricated after a multilevel metalization process is finished.

A version of the cell made in a 0.25-micron process could provide 1 Mb it of memory on a smart card controller with a 20 mm² die size and be mass produced in 2003, Toyoshima said. A version of the cell even further in the future could replace embedded flash in some applications, he suggested.

"One of the biggest problems with ferroelectric technology is scaling, but the NEC guys were trying to tackle the problem of reliability and yields," said Jeffrey Oppold, an ASIC designer at IBM and conference chairman of this year's CICC. "I think there is a market there, but I was surprised to hear how soon they expect to ship products," he said.

Work on the FeRAM cell led to a separate project at NEC on a non-volatile SRAM that could overcome some of the reliability issues of FeRAM by stacking two backup ferroelectric capacitors on a standard six-transistor SRAM cell. The resulting NV-SRAM would store data in the capacitors when the device is turned off.

The NV-SRAM has a higher read/write endurance and faster speed than the FeRAM. It is also suitable for reuse as part of an intellectual property portfolio, while the FeRAM is a custom design. And process technology developed for the FeRAM can be applied to the NV-SRAM.

NEC hopes the new device could open up fresh application areas such as the creation of a non-volatile FPGA. However, the NV-SRAM is still not fully characterized, "so I can't take it to the market yet," Toyoshima said.