Evaluating platform software architectures for nextgen embedded multicore designs

David Kleidermacher, Green Hills Software
8/31/2010 11:07 PM EDT

Imagine: you are the chief software architect of a new embedded design, a decade from now. You are contemplating the microprocessor selected by the hardware guys and bean counters and wondering how in the world you’re going to make best use of its fire power to build the most ambitious product your company has ever conceived.

This SoC has dozens of general purpose processing cores; hundreds of Gbps memory bandwidth across multiple memory controllers; 64-bit addressing; multiple high-speed packet interfaces capable of maxing out numerous 10 gigabit Ethernet interfaces simultaneously; a RAID accelerator; a packet-deduplicator; a compression engine; three-levels of cache; a dizzying array of peripherals (USB, UART, SD card, and more).

In addition it often has a regular expression pattern matching engine; a packet scheduling and routing infrastructure; hypervisor acceleration; a sophisticated security engine with support for symmetric, public key, and hashing; and an amazing suite of on-chip debugging features. The chip reference documentation is many thousands of pages long.

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