English
Survey shows SoC design data management is mission critical
Shiv Sikand, IC Manage
EETimes (10/22/2010 12:02 PM EDT)
Nearly half (47 percent) of IC design engineering and CAD management indicated that design data management issues had caused design and tapeout delays for their organizations. The average delay cited was almost 3 workweeks (14 days).
This is one of the findings of a blind, worldwide survey of 426 IC design professionals on Global SoC Design Management. The majority of the respondents (53 percent) held engineering and CAD management positions. The remaining respondents included digital, full custom and FPGA designers (32 percent), verification engineers (8 percent), and software and firmware developers (7 percent).
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution