English
Making the shift to optical interconnect with PCIe Gen3
Reginald Conley, PLX Technology
EETimes (10/25/2010 1:38 AM EDT)
The highly anticipated launch 8 Gbps, PCI Express 3.0 (PCIe Gen3) is making its debut, doubling the effective bandwidth and generating the same ubiquity and economies of scale as previous generations of PCIe.
With this introduction, PCIe takes its place among the high-performance protocol superpowers – efficiently maximizing gigabits per dollar, port usage and power consumption. But how many gigabits per second is enough? Can copper sustain another bit-rate doubling or have we reached the end of copper links as we know them?
This article will cover the benefits of PCIe Gen3 as an optical interconnect. Along the way, we’ll look at the copper dilemma, optical fibers and pertinent advances in optical technology, such as LightPeak, and its cost/power tradeoffs, and where designers need to focus their attention.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Making the best interconnect choice: weighing the pros and cons
- Shift Left for More Efficient Block Design and Chip Integration
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Network-on-chip (NoC) interconnect topologies explained
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology