English
NVM OTP NeoBit in GLOBALFOUNDRIES (350nm, 250nm, 180nm, 160nm, 150nm, 130nm, 110nm, 65nm, 55nm)
Power Aware Verification of ARM-Based Designs
Ping Yeung and Erich Marschner, Mentor Graphics
11/4/2010 12:49 PM EDT
Power dissipation has become a key constraint for the design of today’s complex chips. Minimizing power dissipation is essential for battery-powered portable devices, as well as for reducing cooling requirements for non-portable systems. Such minimization requires active power management built into a device.
In a System-on-Chip (SoC) design with active power management, various subsystems can be independently powered up or down, and/or powered at different voltage levels. It is important to verify that the SoC works correctly under active power management.
When a given subsystem is turned off, its state will be lost, unless some or all of the state is explicitly retained during power down. When that subsystem is powered up again, it must either be reset, or it must restore its previous state from the retained state, or some combination thereof. When a subsystem is powered down, it must not interfere with the normal operation of the rest of the SoC.
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