Parametric yield: Do you know what you miss?

Yoann Courant, Firas Mohamed, Infiniscale
EETimes (11/10/2010 1:06 AM EST)

Since moving to sub 65-nanometer technologies, Pre-Defined Corners (PDC) verification has attained its limits. The number of corners to verify has become huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design. Some corners could fall inside the process parameters space while others do not really need to be tested.

In this context, EDA has started looking for solutions for this new and key concern. Many solutions have been developed on the back-end side to reduce variability, analyze yield or enhance it. These solutions, although very useful, were not sufficient. Another effort at design level has been made concerning parametric yield. This is thoroughly developed in this paper.

Today, the EDA market offers tools based on the following different approaches: