English
Parametric yield: Do you know what you miss?
Yoann Courant, Firas Mohamed, Infiniscale
EETimes (11/10/2010 1:06 AM EST)
Since moving to sub 65-nanometer technologies, Pre-Defined Corners (PDC) verification has attained its limits. The number of corners to verify has become huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design. Some corners could fall inside the process parameters space while others do not really need to be tested.
In this context, EDA has started looking for solutions for this new and key concern. Many solutions have been developed on the back-end side to reduce variability, analyze yield or enhance it. These solutions, although very useful, were not sufficient. Another effort at design level has been made concerning parametric yield. This is thoroughly developed in this paper.
Today, the EDA market offers tools based on the following different approaches:
- Manual sizing and PDC
- Manual sizing and simulator-based analysis
- Simulator-based sizing and yield optimization
- Model-based sizing and yield optimization
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
New Articles
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
- Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
Most Popular
- Advanced Packaging and Chiplets Can Be for Everyone
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
- System Verilog Assertions Simplified