English
Understanding and selecting higher performance NAND architectures
Doug Wong, Toshiba America Electronic Components, Inc.
Senior Member, Technical Staff
EETimes (12/9/2010 4:31 PM EST)
As NAND Flash process lithographies have decreased to the 30nm and 20nm classes, much higher NAND capacities have become available to meet ever increasing demand for higher density storage in applications from cameras to mobile phones, camcorders, industrial hand-held devices, solid-state drives, and more. However, as capacities have increased, certain aspects of NAND performance have needed improvement, including a need to increase NAND data transfer rates. As a result, memory manufacturers have developed new higher performance NAND architectures to address these issues, such as double data rate (DDR) NAND Flash. Other solutions include NAND with built-in error correction code (ECC) to offload a portion of the host controller requirements, or NAND integrated with a complete controller, such as e-MMC NAND.
This article is intended to help system and memory subsystem designers understand the differences and benefits of some of the newer NAND architectures.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Understanding virtualization facilities in the ARMv8 processor architecture
- Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
- Breakthrough in Microprocessor Architecture and Energy Performance
- USB 3.1 Gen 2 Brings Higher Data Rates with Architecture Improvements
- Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"