SOC: Submicron Issues -> Detailed circuit verification vital for SoC

For instance, ARM cores and MIPS cores are used widely in many communication applications along with embedded memory blocks. Microprocessors are SoC devices, for they typically have on-chip cache memory blocks, phase-locked loops (PLLs) and a number of standard cell blocks. As a result, SoC design has moved beyond its purely digital roots and now increasingly requires high-speed mixed-signal design techniques to improve its verification process. Yet analysis and verification capabilities typically available in conventional EDA env ironments become less and less adequate outside the digital domain.

Traditional design methods and EDA environments approach design verification largely as a front-end activity that works well in digital design for defining a product or verifying functionality in the early stages of the design cycle. HDL-based design with synthesis and digital simulation form the backbone of design and functional verification early in the logic design stages of complex IC development. Nevertheless, traditional digital design has already begun to experience problems in handling mixed-signal SoC in the front end, and has also encountered substantially more difficulties in back-end design verification involving parasitic effects. Many designers find themselves limited in this stage to performing delay calculation with back annotation to high-level digital simulators-approaches that are unable to deal accurately and reliably with the additional complexity of high-speed or low-power nanometer designs.

Successful n anometer SoC design requires significantly better approaches for circuit design, verification and optimization than are generally available in conventional EDA environments. In new designs with feature sizes at or below 0.18 micron, nanometer electrical behaviors arise that simply cannot be captured by conventional digital approaches. First of all, interconnect delay in these designs accounts for 70 percent or more of total delay. In addition, electrical and parasitic effects such as the crosstalk and substrate coupling noises, the inductance effects, the electromigration concern and IR drop of the power net all contribute to increased design complexity and verification difficulty. Together, they rise as a real barrier to delivering first-time working silicon. At high clock frequencies beyond 500 MHz, even pure digital SoC designs begin to exhibit nondigital mixed-signal circuit characteristics including some of the above-mentioned nanometer effects such as inductive ground voltage bouncing.

Unfortun ately, traditional EDA methods typically do not include these electrical and parasitic effects. So they are not equipped to address and to satisfy the nanometer SoC design and verification requirements. As a result, nanometer SoC designs tend to have longer than desired design and verification cycles and more than affordable silicon respins. For designers, the need to resolve these nanometer effects and to ensure first silicon success has become substantially more urgent than ever.

To make a real-world design and verification environment effective, a fast full-chip circuit simulator and analyzer can play a key role because it takes the nanometer effects into account and can simulate and analyze the entire design accurately and efficiently. Such an environment capable of enabling full-chip circuit-level verification requires the database capacity to handle designs ext ending well past 10 million transistors; model and simulation algorithm accuracy sufficient to resolve nonlinear nanometer design and mixed-signal circuit behavior, and high execution performance to provide useful results with acceptable turnaround time for the user. The key circuit simulator thus has to go way beyond the speed and capacity limits achievable by Spice. With it, designers no longer need to partition circuits and simulate smaller circuit segments piecemeal using Spice. Instead, they can understand, verify and optimize the complete circuit behavior.

In particular, SoC design increasingly requires verification of huge post-layout netlists with extracted parasitics to improve full-chip timing and power performance and to increase design margin and product reliability. However, few designers are actually practicing such back-end verification and optimization today due to a lack of post-layout tools and methodology.

In today's SoC environment, more and more designers need to deal wit h designs with tens of millions of transistors and growing. The sheer size of these massive designs limits the full-chip verification approaches to two basic options: mixed-level or hierarchical.

In mixed-level approaches, design representations are maintained at different levels of abstraction and elaborated as details become available. Although this is useful in front-end design, it does not help for detailed full-chip verification to ascertain the correct circuit implementation in the physical design. Neither does it ensure working silicon for the design. This is mainly because the mixed-level simulators do not have the capacity and sometimes accuracy to handle large numbers of low-level circuit elements.

Yet the real circuit response at that detailed low level, which often differs from the front-end model prediction because of parasitic or interface effects, will determine the true behavior of the final silicon product. As a result, designers cannot rely on conventional mixed-level verifi cation tools to ascertain nanometer design success.

Hierarchical approaches can more easily deal with capacity problems, because a hierarchical verification tool does not need to store every design element in memory. Instead, hierarchical circuit simulation tools such as Nassda's HSIM (Hierarchical Simulator) need only store single templates of distinct circuit elements for each design. For HSIM, memory storage efficiency is obtained by instantiating specific instances from the templates as needed in simulating circuits with regular structures or repeated elements such as memory, data path circuits or even standard-cell functional blocks built from cell library elements.

Although hierarchical storage helps minimize memory usage in HSIM, a new solution algorithm is implemented to solve Spice equations hierarchically to gain a substantially higher simulation speed. As a result, HSIM has a very high circuit-capacity limit and can run circuit-level simulations at three to four orders of magnitude faster than Spice-permitting full-chip circuit simulation of SoC-class designs with accuracy close to that of Spice. Indeed, HSIM can complete full-chip transistor-level verification of a large circuit such as a 256-Mb DRAM memory design comprising over 300 million elements in a matter of hours on a PC. It simulates mixed-signal SoC design with a similar efficiency because of the on-chip memory blocks and regular structures existing in such designs.

Designers can take advantage of the new breed of hierarchical tools without disrupting their current design processes. For a typical design, the engineer has already established hierarchical partitioning from the earliest stages of design, when design elements such as memory blocks, glue logic and bus structures are captured hierarchically in the netlists in terms of nested subcircuit instantiations.

More importantly, without forcing any particular hierarchical structure, HSIM can back-annotate extracted layout parasitics in Detailed Standard Par asitic Format (DSPF) onto a hierarchical prelayout netlist. This post-layout verification process will save storage space significantly while simulating all the parasitic effects in details. It allows designers to look at the post-layout circuit behavior in an environment where design hierarchy and subcircuit definitions remain unchanged with respect to those in the very familiarized prelayout environment. Post-layout problems can be more easily identified and resolved, and design can be optimized, vs. the large post-layout Spice netlist obtained from flat extraction.

Full-chip circuit-level verification is vital for nanometer SoC designs as designers take on designs comprising tens of millions of transistors influenced by nanometer effects and analog and memory components. Current digital-centric approaches that depend on limited circuit simulation will prove less and less effective as digital and analog memory elements converge more rapidly in high-end SoC designs. In these increasingly mixed-signa l SoC designs, detailed full-chip circuit-level verification will provide critical information for verifying design functionality at implementation, optimizing timing and power, correcting nan-ometer electrical effects and ensuring the silicon success of nanometer SoC designs.