English
55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Multiband architecture for high-speed SerDes
Christian Weber, Jinjin He, Lizhi Charlie Zhong, and Huaping Liu
EETimes (1/20/2011 3:45 AM EST)
Abstract
As the speed of serializer/deserializer (SerDes) increases (e.g., to 25 Gbps and above), the channel will cause more severe inter-symbol interference. Design of low-complexity transceivers for such high-speed SerDes faces many technical challenges. In this paper, we explore a multiband architecture for a 25 Gbps SerDes, where the channel in each sub-band is approximately frequency flat, eliminating need of an equalizer in the receiver. Since different bands experience different signal attenuations, the power level for each band can be adjusted accordingly to minimize the average transmission power. A multiband transceiver is designed, and analysis and simulation results for various choices of parameters (bands, modulations, etc.) are presented.
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