English
Key factors for success in dealing with Asian fabs
Raj Kumar
EETimes (2/22/2011 4:02 PM EST)
Managing business during an economic upturn could be more challenging than in a downturn. It is currently the case in the semiconductor industry where more than the supply and demand law is keeping every manager in the whole supply chain on his/her toes. While production management is dealing with capacity ramping in the existing fabs without investing much in new plants, sales marketing and logistics managers are engaged in setting equations to take advantage of the situation by allocating capacities to higher margin products and distributing volumes to strategic customers. In this fab-tight situation, conditions are not much different for foundry interface managers of IDM (Integrated Device Manufacturers) and fabless companies. Foundry interface engineers and managers (referred to as FIP-Foundry Interface Personals) of fabless and IDM/fab-lite companies (referred to as “design house” in subsequent text) are struggling to ensure volume capacity at foundries.
In the current fab-tight situation, capacity may be the main topic. In normal business, cost, quality, speed and volume scaling are other key result areas (KRA) for foundry interface managers (FIPs). As shown in Figure 1, the mutually conflicting nature of these four factors makes the common area very small. FIPs' main challenge is to find a sweet spot where all needs are met. Foundries, in principle, ought to respond to all customers’ needs and share true information. However, in the real world, other situations and conflicts of interest may prevail and influence the outcomes.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification