English
Planning reset strategy: Flow & functionality in OVC
Parag Goel, Pushkar Naik, Applied Micro Circuits Corp.
3/9/2011 8:01 AM EST
Overview
Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/system and is the first step in the sequence of operations done for any system bring up. The following write-up addresses this essential strategy to be followed during verification using an OVM-based test bench.
While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- SoC tool flow techniques for detecting reset domain crossing problems
- Optimize SoC Design with a Network-on-Chip Strategy
- An Outline of the Semiconductor Chip Design Flow
- Maven Silicon's RISC-V Processor IP Verification Flow
New Articles
Most Popular
- Streamlining SoC Design with IDS-Integrate™
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- PCIe error logging and handling on a typical SoC