Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
Graham LS Connolly, Principal Engineer, and Tony Lee, Applications Engineer, Fairchild Semiconductor Corp.
3/16/2011 1:08 PM EDT
(Part 1 looked at the nature of the problem, as well as the requirements of D-PHY MIPI® dual camera/dual display applications, click here to read it.)
What is the solution?
The solution is to add an analog switch.
When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good “eye” performance by minimizing reflections and edge rate degradation. Initially, the extra CON/COFF of the switch may be viewed as a detriment to the system performance, but in reality, removing the discontinuity reflections outweighs the extra capacitance and series resistance incurred by inserting the analog switch. The MIPI specifications use a 0.3 UI (unit interval) for the criteria of Interoperability, so the faster you want to run your system, the more critical the switch CON/COFF characteristics becomes, since that is the parameter that will impact the edge rate and, therefore, the 0.3 UI criteria.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
- Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications
- Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays
- A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY
- All you need to know about MIPI D-PHY RX
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)