How to achieve quality assurance for your electronic designs
Clive Maxfield, EETimes
4/4/2011 11:22 AM EDT
It’s no secret that electronic designs are becoming ever more complex. I used to think things were hard enough back in 1980 when I was designing my first ASIC as a gate-level schematic using pencil and paper. Looking back, however, I realize life was a doddle and I had things easy – all I had to worry about was making sure the logic was functionally correct and would fit in the device (a gate array containing 2,000 equivalent gates) and that the timing was OK, which wasn’t particularly taxing since our system clock was sub-1MHz and we had lots of slack to play with.
We didn’t even think about things like leakage power and dynamic power consumption. Now, of course, we’re talking about designs containing millions upon millions of logic gates, including humungous blocks of third-party IP, more processor cores and hardware accelerators than you can swing a stick at, with millions of lines of software thrown into the mix.
So how do we ensure the quality of all aspects of an electronic design, including hardware (digital, analog, mixed-signal...) and software (boot code, test routines, firmware, drivers...) for anything from FPGAs and SoCs to full-blown embedded systems?
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- ipPROCESS: A Usage of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi Project Environment
- How to defend against the cloning of your FPGA designs
- How to choose an RTOS for your FPGA and ASIC designs
- How to use register retiming to optimize your FPGA designs
- Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
New Articles
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
- System level on-chip monitoring and analytics with Tessent Embedded Analytics
- What tamper detection IP brings to SoC designs
- RISC-V in 2025: Progress, Challenges,and What's Next for Automotive & OpenHardware
Most Popular
- System Verilog Assertions Simplified
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- How to Design Secure SoCs: Essential Security Features for Digital Designers