Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP
Scaling a video on demand server
Early performance estimation is key to successful implementation
Illia Cremer, CoFluent Design
EETimes (4/27/2011 9:51 AM EDT)
Abstract
In a growing and more competitive video on demand (VoD) market, system designers face new challenges in VoD server infrastructures definition and sizing. Early performance estimation thanks to abstract modeling is a key enabler for providing best quality of service and compelling user experience.
This article illustrates how to model and simulate an example model of a RTP/RTSP video on demand server using the method, notations and tools provided by CoFluent Design.
The objective is to determine the client’s frame rate deviation and the average power consumption for different server configurations. The frame rate deviation is the difference between the expected theoretical frame rate and the actual frame rate of the video stream. It directly impacts the user’s watching experience and should be kept as much as possible close to zero.
The impact of different hardware elements of the server such as HDD type and server buffering is studied. The example also illustrates how to model multiple instances of the same function, and how to define an abstract network of computers.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Polyphase Video Scaling in FPGAs
- Using vector processing for HD video scaling, de-interlacing, and image customization
- AI-driven SRAM demand needs integrated repair and security
- Applications And Operations of Video Analytics
- VESA Video Compression on MIPI DSI-2 Enables Next-Generation Display Applications
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology