Reality hampers vision of interoperable IP cores

Reality hampers vision of interoperable IP cores
By Junko Yoshida, EE Times
March 6, 2002 (4:58 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020305S0044

PARIS — Although the worldwide market for semiconductor intellectual property (IP) is growing 20 percent a year, the electronics industry's efforts to establish open IP trading have been hindered by instability and self-recrimination, according to panelists at the Design Automation and Test in Europe conference in a session titled "The Real Cost of Acquiring IP — The Invisible Factor Holding Back Buyer's Usage and Seller's Profits."

The lack of "verifiable" standards, poorly-made IP that doesn't map well into silicon and IP vendors perceived as unstable are among the issues holding back the industry's vision of openly available, interoperable, plug-and-play IP cores, said the panel.

Further, the industry may have vastly underestimated what's needed to implement a system of reusable virtual components, some panel members suggested.

Speaking from the audience, Larry Rosenberg, technical chairman of the Virtual Socket Interface Alli ance (VSIA), said, "The idea of virtual components that are reusable in any environment without redesign was naive." Individual IP cores have too many unpredictable elements that are hard to change or fix when dropped into a system-level design, he said. Dealing with IP blocks is "a little bit too low level," Rosenberg said. "We have to move up a level to a platform design." The VSIA has just launched a study group on "platform design" to explore how it may help the reusability of virtual components, he said.

Panelist Andy Travers, chief executive officer at Virtual Component Exchange (VCX), agreed. "To design an interoperable system quickly just by plugging in reusable, independent IPs together was a self-fulfilling fantasy created by the demand side," he said. Some of the standardization work carried out within the VSIA has exposed some complex underlying technology issues, Travers said. In designing a system, "low-level individual IPs must be handled in a bigger context, involving both software and so me kind of platform approach."

Asked which standards must be further specified to set IP trading in motion, Tim Daniels, ASIC product marketing manager at LSI Logic Europe (Berkshire, United Kingdom), said that testbenches are "still a big issue," lacking sufficient external standards. "IP is not a dog food sold in a supermarket," Daniels said. "IP has to come with a rigorous methodology and testbench so that we can make sure the IP works in an FPGA, and eventually in an ASIC."

Agreeing with Daniels' assessment of testbench standards, Pierre Bricaud, responsible for SoC strategic relationships at Mentor Graphics Europe (Sophia-Antipolice, France), said, "Standards must be verifiable and checkable."

The matter is complicated further, VCX's Travers said, because "there is a vast range of interpretation of standards."

Jim Tully, chief analyst of the Semiconductor Group at Gartner Dataquest (Surrey, United Kingdom), asked the panel why there are so far no takers on evaluation services for IP. The panelists answered by saying that IP buyers demand "proof" first and foremost. "We've heard it loud and clear from many IP buyers, especially from Japan, that they won't talk to IP providers unless they've seen it in hardware," said Travers.

Pat Mead, technical marketing manager at Altera Europe (Buckinghamshire, United Kingdom), advised IP vendors, "Get yourself a programmable platform. Building [your IP] on an FPGA will serve as a huge confidence builder and raise the visibility of your IP."

Mentor's Bricaud bluntly noted, "If it hasn't seen hardware, your IP won't be worth much."

All the panelists agreed that the Web is an ideal way for cataloging IP resources, but many remained unconvinced it is the best forum for IP negotiations or post-sale services. John Heighton, with IP and services marketing at Xilinx Europe (Surrey, United Kingdom), noted that poorly made IP in particular requires a strong support team to sort out integration and interaction issues involving other blocks on a chip.

But some users are leveraging intranets to build a repository of third-party and internal IP, including Alcatel. Thierry Pfirsch, core competence manager for intellectual property at the ADSL ASIC Design Labs of Alcatel (Zaventem, Belgium), said that different groups within his company put a piece of IP from a third party through their own certification and qualification processes, then put the results on Alcatel's intranet for others to see. "We think this is an important discussion forum to exchange information inside our company," Pfirsch said.