It's not just about hardware anymore
Donald Cramb, Director of the Consulting Services Division of EVE-USA
EETimes (5/25/2011 12:10 PM EDT)
The poor person tasked with designing and delivering a processor today has a tough job. Much tougher than his or her forebears of just a couple decades ago.
In the hierarchy of systems, the processor has always played a central role. When making architectural decisions on a system, one of the first considerations is which processor to use. Once chosen and configured, a designer can go about implementing the agree-upon structure. The key question is, how do you know when you’re done?
That’s where things have gotten tough. The basic expectations of what it means to have a working chip have changed dramatically with the advent of the system on a chip (SoC). And, to the chagrin of designers, those expectations have gone way up. The verification required to meet this higher standard has evolved to the point where, before silicon is delivered, software must be executed. This burns through so many clock cycles that the only way to prove with any confidence – and in a reasonable timeframe – that software works is through emulation.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Analyzing the Options in High-Bandwidth System Interconnect-or, Serial: It's Not Just for Breakfast
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- Radiation Tolerance is not just for Rocket Scientists: Mitigating Digital Logic Soft Errors in the Terrestrial Environment
- It's Not My Fault! How to Run a Better Fault Campaign Using Formal
- This Isn't Your Father's JTAG Anymore
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)