Two methodologies for ASIC conversion
Ron Wilson, EETimes
5/31/2011 2:30 PM EDT
ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a cell-based ASIC, further illuminates some of the important choices that come up in reworking an existing design. The two approaches are conceptually similar, but practically quite different.
Structurally, the design problems the two companies face are similar. KaiSemi converts a working FPGA design into a cell-based ASIC design. Similarly, eASIC converts a Nexstreme or Nexstreme-2 structured device design - which may or may not have originated in an FPGA - into a cell-based design. Both strive to offer a turnkey service in which the customer has to understand very little of the ASIC process beyond RTL verification and timing.
E-mail This Article | Printer-Friendly Page |
Related Articles
- How to get the best cost savings when implementing an FPGA-to-ASIC conversion
- ''Do's and Don'ts" when considering an FPGA to structured ASIC design methodology
- FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM
- FPGA-to-ASIC conversion a crucial concern
- Build Complex ASICs Without ASIC Design Expertise, Expensive Tools - Take advantage of an architecture comparable to your original FPGA prototype design by migrating to a structured ASIC
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)