3-D IC design: New possibilities for the wireless market

Samta Bansal, Brad Griffin and Marc Greenberg, Cadence
EETimes (6/7/2011 1:29 PM EDT )

Today’s mobile devices are about having everything in the palm of your hand, at the touch of a button—from Internet browsing and e-mail to watching high-definition TV or using a GPS. Increasing demand for multimedia features translates into complex design requirements, such as higher performance with reduced power in an ever-smaller footprint.

Design teams have two choices: either shrink the node or innovate some alternative to address the “more than Moore” trend. With development costs heading toward $100 million for the 32-nanometer process node, for example, monolithic mixed-signal SoCs are increasingly challenging and time-consuming to develop.

Design teams are looking for alternatives to speed time-to-market and reduce costs, and some are finding that using 3-D ICs with through-silicon vias (TSVs) represents the most practical way—or perhaps the only way—to handle design complexity and maximize performance and speed. 3-D ICs promise to meet market demand for miniaturization, higher speed and greater bandwidth, as well as lower latency and power consumption. That makes the move from 2-D to 3-D a natural choice.

The question today is not whether 3-D ICs will be designed and built, but whether design teams (outside of a handful of large semiconductor companies) will have the EDA tools and infrastructure support required to make 3-D-ICs cost-effective.

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