Aeonic Generate Digital PLL for multi-instance, core logic clocking
Guide to VHDL for embedded software developers: Part 2 - More essential commands
Peter Wilson
EETimes (7/19/2011 10:35 PM EDT)
Editor’s Note: In this series of articles based on his book – Design Recipes for FPGAs – Peter Wilson provides a basic quick overview of VHDL (VHSIC hardware description language) followed by examples of its use in describing - in HDL code form - functions familiar to most embedded software developers such as arithmetic logic units (ALUs) and finite state machines (FSMs). It is not intended as a comprehensive VHDL reference. For that, he recommends “Digital System Design with VHDL,” by Mark Zwolinski; ”VHDL: Analysis and modeling of digital systems,” by Zainalabedin Navabi or “Designer’s Guide to VHDL” by Peter Ashenden.
In hierarchical designs, functions are a simple way of encapsulating behavior in a model that can be reused in multiple architectures. Functions can be defined locally to an architecture or more commonly in a package.
E-mail This Article | Printer-Friendly Page |
Related Articles
- A guide to VHDL for embedded software developers: Part 1 - Essential commands
- Guide to VHDL for embedded software developers: Part 3 - ALU logic & FSMs
- Optimizing embedded software for power efficiency: Part 2 - Minimizing hardware power
- Leveraging Virtual Platforms for Embedded Software Validation: Part 2
- An architecture for designing reusable embedded systems software, Part 2
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- System Verilog Assertions Simplified
- Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP)
- Dynamic Memory Allocation and Fragmentation in C and C++
- Synthesis Methodology & Netlist Qualification