Selecting clock skews at advanced nodes

Ravi Chhabra, Srijith Nair, & Ekta Gujral, Freescale Semiconductor
EETimes (7/25/2011 11:55 AM EDT)

As a designer, it is the general tendency to minimize skews and have a perfectly balanced clock tree. Zero skews are not always good for the design as it may result in very high dynamic power consumption as all the flops and buffers will be toggling at the same time. As technology is shrinking and frequency is increasing, the impact magnifies. Also minimizing skew comes at a very big cost of power, congestion and thus die area. In this paper we propose the optimal criteria for selection of skew number to minimize power, congestion and, at the same time without any compromise in timing across all the corners. By optimal selection of skew number we are able to reduce the clock power consumption by 15%, clock buffer count by over 30% and significant congestion reduction with similar timing summary across all the corners.

Introduction Robust clock tree designing is the biggest hurdle in high frequency designs. With shrinking technology and increasing frequency, the clock tree consumes an increasing fraction of resources such as design time, power, and wiring [9]. It decides the robustness of the design as well. While designing the clock tree, designers target perfectly balanced clock tree with minimum possible skew. While this ensures that all the flops capture the data at the same time yet this leads to very high peak dynamic power m dissipation. Due to simultaneous switching of high frequency clock signals, it also causes EMC-EMI failures.

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