English
ICE-IP-338 High-speed XTS-GCM Multi Stream Inline Cipher Engine
Latches and timing closure: a mixed bag
Ashish Goel & Ateet Mishra, Freescale Semiconductor
EETimes (8/2/2011 3:29 PM EDT)
Introduction
Digital blocks contain combinational and sequential circuits. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the combinational circuits depends only on the present input. Latches and flip flops are the commonly used storage elements.
This paper is divided into 4 parts. First part of the paper will discuss the advantages and disadvantages of latches compare to Flip-Flop. Next part describes some unique properties of latches that make them useful in high-frequency design. Third part of the paper will talk about the timing analysis complexities for latch-based design and how to deal with this complexity during the course of design. Finally, the paper will discuss challenges with latch-based design to hierarchical timing closure and partitioning, and some solutions.
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