English
Get control of ARM system cache coherency with ACE verification
Mirit Fromovich, Pete Heller, and Yoav Lurie, Cadence
EEtimes (8/9/2011 1:34 AM EDT)
In this Product How-Two article, the Cadence authors describe how to use the company’s Verification IP solutions framework to implement ARM’s AMBA 4 Coherency Extensions (ACE) in embedded SoC designs.
The challenges facing designers of the next generation of devices such as multimedia smartphones, tablets, and other mobile devices are many. They have to deliver highly responsive systems yet must also consume the least power possible—certainly no more than their competitors.
To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need for even greater performance has exceeded the capability of current multi-processor/multi-cluster architectures.
Squeezing every last drop of performance and power out of these compute clusters is more important now than ever. One of the largest areas of opportunity for performance gains in multi-processor systems is in moving software-based cache-coherency management into hardware.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Cadence Design Systems, Inc. Hot IP
Related Articles
- ACE'ing the verification of a cache coherent system using UVM
- Fast, Thorough Verification of Multiprocessor SoC Cache Coherency
- Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol
- SoC design: When a network-on-chip meets cache coherency
- Arteris System IP Meets Arm Processor IP
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow