English
NVM OTP NeoBit in Maxchip (180nm, 160nm, 150nm, 110nm, 90nm, 80nm)
Cache-Coherence Verification
Rajeev Ranjan, CTO, Jasper Design Automation
8/17/2011 11:38 AM EDT
As consumers, we place many demands on our personal electronics, especially mobile devices. We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption. Complex embedded SoCs have largely enabled the functional capabilities of these devices. To ensure that these devices perform at a desired level to accomplish the tasks needed, today’s embedded SoCs must consist of high-performance, heterogeneous, and multi-processing agents. The presence of a large number of data processing agents sharing a memory resource on an SoC requires that the agents maintain some type of locally cached data to reduce the data transportation cost. This, in turn, leads to the requirement for cache coherency to allow agents to cache data during processing and then make it available to the next processing agent.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Early Interactive Short Isolation for Faster SoC Verification
- Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality
- Why verification matters in network-on-chip (NoC) design
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)