Many-Core: Finding the Best Multi-Processing Tile
Omar Hammami, Associate Professor, ENSTA ParisTech & Ludovic Larzul, Vice President of R&D, EVE
EETimes (8/29/2011 4:01 PM EDT)
Very few people design with transistors these days. Everyone creates systems that contain transistors, but your average designer, while obviously being aware of that fact, wouldn’t know much about the intimate details of the transistors being used, aside from sizing or ratios.
And that’s intentional. It’s the result of the inexorable wave of abstraction. Transistors became gates became cells became IP. And one particularly important IP block is the microprocessor.
Today you can purchase a microprocessor IP block, configure it, and commit it to silicon without having to worry about the underlying logic, not to mention the transistors implementing that logic. Depending on the processor you choose, you will automatically inherit an entire ecosystem of companion IP as well as software infrastructure for implementing your application. All thanks to abstraction.
But it’s got further to go. We’re already in the multicore world, and, following on its heels, is the “many-core” world, which is the same as multicore, but dives right in with lots and lots of cores instead of timidly sticking its toes in with just two or four.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow