Using SystemVue to overcome 4G challenges
Daren McClearnon and Wu Huan, Agilent Technologies
12/5/2011 9:59 AM EST
LTE-Advanced (LTE-A) is an emerging mobile communications standard being developed by 3GPP. Specified as part of Release 10 of the 3GPP specifications, it is now approved for 4G IMT-Advanced. LTE-A leverages many existing LTE Release 8/9 parameters, while also incorporating a number of enhancements, including carrier aggregation, an enhanced multiple access scheme and MIMO transmission, multi-hop transmission, coordinated multipoint (CoMP) transmission/reception, and support for heterogeneous networks. These enhancements enable significant benefits, but they also create baseband and RF design challenges that further complicate the 4G physical layer (PHY) architecture development. Next-generation Electronic Design Automation (EDA) tools, with their array of new capabilities, offer a viable resolution to this dilemma. The trick is in understanding what these new capabilities are and how they can be used to overcome 4G challenges.
A number of EDA tools available on the market today can be used for LTE-based design; however, creating superior systems designs for the emerging LTE-A standard requires an entirely new set of functionality.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I)
- Overcome signal attenuation, noise and jitter interference challenges in USB 3.0 system design
- Overcome power, size and cost when developing optimized '4G' chipsets for handhelds
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Key considerations and challenges when choosing LDOs
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow