Code Coverage is Crucial in the IP Qualification Process
The Challenge of Verifying Configurable IP
Silicon intellectual property (IP) providers face a rising number of challenges in providing fully verified cores to their customers. IP users expect cores to be fully verified and robust in every usage scenario. In verifying their IP, providers must therefore try to anticipate each and every situation a core will encounter when integrated into a customer's system. Increased complexity and size mean a staggering number of test cases must be run to successfully verify an IP, and it must be done as quickly and economically as possible. This challenge is multiplied when the core in question is customer-configurable, with thousands of potential configurations.
Since configurable IP is so difficult to verify, why create it in the first place? The benefits are numerous. For the IP vendor, it means having just one master core to develop and maintain, instead of thousands of variant cores. For the IP user, there is the flexibility to reconfigure the core on the fly to meet the changing needs of project. If a design specification changes, requiring a change to the core, a traditional reusable core would have to be replaced, redesigned or designed from scratch. A configurable core, on the other hand, is easily adaptable. User-configurability also minimizes or eliminates the need to perform detailed RTL modifications by hand to meet design requirements. And once configured, these cores exactly meet SoC requirements.
When an IP vendor is developing configurable IP, they have to bear in mind not only the complexity of the task, but also the constraints of time and budget. Customers face shrinking market windows and the challenge of integrating their own IP with third party IP of which they have no first-hand knowledge. They need to know that a chip is fully verified and will be bug-free in all possible scenarios.
With these challenges, how can a vendor verify a core enough to be able to say with any degree of certainty that it will perform as expected in any configuration? Given unlimited time and resources, the vendor could create tests for each scenario. But we all know that time is anything but unlimited. And the vendor must not only make sure that the core is bug-free, but must also enable the customer to integrate the core into their system quickly and at the lowest cost possible.
Related Articles
- Improve functional verification quality with mutation-based code coverage
- OCP VIP: A cost effective and robust qualification process for multimedia and telecom SoC designs
- Creating, Simulating, and Debugging SVA Code Outside of the Traditional Design/Verification Environment
- Building more secure embedded software with code coverage analysis
- DO-254 for Dummies: IP & verification process
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
E-mail This Article | Printer-Friendly Page |