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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
PowerSoC solves switch-mode DCDC noise and space issues
Michael Laflin, Enpirion, and Austin Lesea, Xilinx
EETimes (2/5/2012 5:00 PM EST)
Introduction
Conversion efficiency is driving FPGA system designers away from the use of linear regulators and toward the use of switch mode DCDC converters. While switch-mode DCDCs offer dramatic increases in efficiency, they also require a much more complex design, increase part count and footprint, and most significantly for high-speed IO, switch-mode DCDC converters are a source of noise.
This article describes the various components of noise in a switch-mode DCDC converter and demonstrates how PowerSoCs can minimize those components. The article further shows design examples and demonstrates how PowerSoCs can power high speed IO with performance equivalent to or better than Linear Regulators.
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