English
Considerations for writing UPF for a hierarchical flow
Jeffrey Lee and Mary Ann White (Synopsys)
4/6/2012 11:01 AM EDT
Introduction
Writing power intent for a design using the IEEE 1801 Unified Power Format (UPF) is generally an easy and straight-forward task. If the design will be optimized in a flat fashion (e.g. the entire design is optimized top-down in a single session), then writing the power intent is fairly simple.
Situations such as being too rigid in where your power management cells need to be implemented and writing power intent for hierarchical designs can make writing UPF a much more difficult task. This article details the considerations that you need to take into account when writing UPF for a hierarchical design methodology.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- An Outline of the Semiconductor Chip Design Flow
- Design Rule Checks (DRC) - A Practical View for 28nm Technology
- Synthesis Methodology & Netlist Qualification