Considerations for writing UPF for a hierarchical flow
Jeffrey Lee and Mary Ann White (Synopsys)
4/6/2012 11:01 AM EDT
Introduction
Writing power intent for a design using the IEEE 1801 Unified Power Format (UPF) is generally an easy and straight-forward task. If the design will be optimized in a flat fashion (e.g. the entire design is optimized top-down in a single session), then writing the power intent is fairly simple.
Situations such as being too rigid in where your power management cells need to be implemented and writing power intent for hierarchical designs can make writing UPF a much more difficult task. This article details the considerations that you need to take into account when writing UPF for a hierarchical design methodology.
E-mail This Article | Printer-Friendly Page |
|
Synopsys, Inc. Hot IP
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)