Changing the paradigm for TV silicon tuners
Melissa Chee and Scott Howe, Fresco Microchip
EETimes (4/24/2012 10:09 AM EDT)
Although the TV market continues to mature, the underlying architectures inside the television continue to evolve to drive down prices. "Cost-down" are the two most spoken words in consumer electronics. Increasing cost pressure drove architectural shifts that led to rapid consolidation in the system-on-chip (SOC) market and accelerated adoption of silicon tuners in the television. The ability to achieve the lowest cost system solution without compromising performance requires disruptive technology. This article will look at key TV market trends and their effect on next-generation TV front-end solutions.
Changing TV landscape
Every year more than 250 million TVs ship into analog only and hybrid (analog plus digital) markets worldwide. By the end of 2011, a select few SOC companies accounted for the vast majority of all TVs shipped. The most popular SOCs have integrated functions that are implemented most cost-effectively in the digital domain. At the same time, many silicon tuners have retained this functionality using expensive RF/analog processes, which adds unnecessary system cost and complexity.
Traditionally, many CAN tuners were MOPLL-based (Mixer Oscillator Phase-Locked Loop). As the cost/performance tradeoff improves, silicon tuners are rapidly replacing MOPLLs and are projected to approach nearly 100 percent market penetration in television within the next 18 months. Designing silicon tuners directly on the main TV printed circuit board (PCB) and in the CAN are both common – the implementation depends on the relative RF expertise of the TV maker.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)