Expanding emulation's reach with virtual devices
Jim Kenney, Mentor Graphics
EETimes (6/3/2012 11:38 PM EDT)
With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware.
The increasing prevalence of complex, multifunctional, networked devices and the rising importance of embedded software create a need for faster simulation run times and full system verification early in the design cycle (Figure 1, below). Hardware-assisted verification, or emulation, delivers the required capacity and performance for extremely fast, full SoC testing—hardware and software. However, for many, a prosaic barrier to the benefits of emulation has proven both stubborn and persistent. The high-cost of emulators has made them affordable only for companies with deep pockets.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution