English
Fully Depleted Silicon on Insulator devices
Brian Bailey, EETimes
6/19/2012 11:37 AM EDT
For decades, we rode the technology wave by building smaller and smaller transistors into a bulk silicon wafer. Around 90nm, we began to realize that there were problems ahead as voltage scaling slowed and leakage currents increased. Small changes were made in the process to lengthen the bulk lifetime, but there are reasons to look at completely different ways to build circuitry, especially at the latest geometries of 28 and 20 nm. Once such possible way forward is Fully Depleted Silicon of Insulator (FD SOI). Researchers believe that this technology will scale down to 11nm.
FD SOI relies on an ultra-thin layer of silicon over a Buried Oxide layer. Transistors built into this top silicon layer are Ultra-Thin body devices and have unique, extremely attractive characteristics according to Soitec, a manufacturer of the wafers needed to build these products. I spoke to Soitec’s Steve Longoria – SVP Business Development, who walked me through some aspects of the technology.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
- How to cost-efficiently add Ethernet switching to industrial devices
- Fully Automating Chip Design
- High Speed, Low Power and Flexibility Drive DisplayPort's Increasing Popularity
- Upskill Your Smart Soldiers and Conquer the ChipWar in Style!