English
Prevention, quality and other innovations in hardware debug
Neil Johnson, XtremeEDA Corp
EETimes (7/2/2012 12:08 PM EDT)
Debug represents a major cost to hardware development organizations and a constant source of frustration for engineers. According to a survey commissioned by Mentor Graphics in 2010, verification engineers spend an estimated 32% of their time debugging code[1]. In a typical 8-hour day, that translates to more than 2.5 hours specifically dedicated to fixing defects.
Spending 2.5 hours debugging code can make for a frustrating day for an engineer, but what does that mean for the organization? According to the EE Times Global Salary and Opinion Survey from 2010, the annual compensation for a North American engineer, including bonuses and overtime pay, averaged $107,300[2]. From that, it’s easy to make a best case, back-of-the-napkin estimate capturing the cost of employing a medium sized team of engineers to build a reasonably sized ASIC. The result is a very big number.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Using emulation to debug software and hardware at the same time
- Integration drives embedded software development and hardware debug
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
- Optimizing Automated Test Equipment for Quality and Complexity
- Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality
New Articles
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution