What Your SoC Designer Might Not Tell You About Power Management

By Ron Wilson, Editor-in-Chief, Altera Corporation

System designers today are beneficiaries of the enormous effort that system-on-chip (SoC) designers have put into chip-level power management. But for systems to actually consume less energy, system design teams must know what their SoC’s power management actually does. They must have a power plan for the overall system. And they must have an accurate model of the use modes their system will experience at the hands of end users. None of these are easy tasks, but taken together they are still not enough. System designers must understand the interactions between on-chip power-management processes and the rest of the system, or they may find that trying to save power can lead to lowered efficiency or even serious malfunctions.

These challenges will not be getting easier. Chip designers are looking under every rock, and prodding every radical-sounding idea in their search for greater energy efficiency. “There is a big list of techniques, and we are moving toward using all of them,” said TI fellow Clive Bittlestone during a panel at this year’s Design Automation Conference (DAC). As chip designers pursue power savings into the underbrush of diminishing returns, they can inadvertently complicate life for system designers. Yet system design is the new frontier for energy savings. “We’ve about reached saturation at the transistor level,” Bittlestone admitted. “The next big thing is the system level.”

Click here to read more ...

E-mail This Article

Printer-Friendly Page

Contact Intel FPGA Fill out this form for contacting a Intel FPGA representative. Your Name: Your E-mail address: Your Company address: Your Phone Number: Write your message: