Optimizing PCIe SSD performance
Shawn Kung, Marvell Technology and Larry Chisvin, PLX Technology
EETimes (8/20/2012 3:38 PM EDT)
Server-side solid state drive (SSD) deployment in the enterprise market is growing by 55% per year and is expected to reach nearly 10 million units annually over the next several years according to Gartner Research. In applications such as transactional processing, data search, and data mining, the higher performance of SSDs offers tangible, real-world benefits. The cost of NAND flash has been moving steadily downward, and the number of companies servicing this market has been increasing. Because of this, differentiation on value (rather than price) is becoming more difficult, but value is the primary mechanism for storage solution providers to win and sustain their business.
Server and storage systems vendors can add value to what they provide to their customers in the form of performance, scalability, and reliability via their software and hardware architecture. In order for these complex systems to function at their peak, however, two of the largest contributors to these added values—the SSD controller and interconnect—need to be matched and tuned. At the most fundamental level, component vendors need to share a common vision of how a system should be designed and deployed. One of the most important decisions is the interconnect used to get the data from storage to host. PCI Express (PCIe) is rapidly becoming a key interconnect in enterprise SSD storage, and is expected to account for more than one-third of the server SSD market by 2015, according to Gartner.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- High-Speed PCIe and SSD Development and Challenges
- Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
- Conquering the challenges of PCIe with NVMe in order to deliver highly competitive Enterprise PCIe SSD
- Optimizing Sensor Performance with 1T-OTP Trimming
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)