English
Design workflow management enhances SoC design quality and efficiency
Albert Li, Director, Reed Lee and Louis Liu, Manager Global Unichip Corp.
EETimes (8/20/2012 11:29 AM EDT)
Every semiconductor company and for that matter, every technology company constantly juggle a number of designs that are at different stages of development. To handle the numerous challenges, semiconductor companies in particular need to define a design workflow management system whose mechanisms adopt to a number of design and business models and can resolve the challenges of working on multiple designs from multiple locations.
Design collaboration (Figure 1) is the obvious but sometimes difficult given growing design complexity. Design teams and team members are located in different geographical regions and face complex design, data management and flow integration challenges. A tradeoff between schedule and quality is the major concern.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency
- System-on-chip (SoC) design is all about IP management
- How NoCs ace power management and functional safety in SoCs
- Analog and Power Management Trends in ASIC and SoC Designs
- Breaking new energy efficiency records with advanced power management platform
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)