7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Design workflow management enhances SoC design quality and efficiency
Albert Li, Director, Reed Lee and Louis Liu, Manager Global Unichip Corp.
EETimes (8/20/2012 11:29 AM EDT)
Every semiconductor company and for that matter, every technology company constantly juggle a number of designs that are at different stages of development. To handle the numerous challenges, semiconductor companies in particular need to define a design workflow management system whose mechanisms adopt to a number of design and business models and can resolve the challenges of working on multiple designs from multiple locations.
Design collaboration (Figure 1) is the obvious but sometimes difficult given growing design complexity. Design teams and team members are located in different geographical regions and face complex design, data management and flow integration challenges. A tradeoff between schedule and quality is the major concern.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- System-on-chip (SoC) design is all about IP management
- How NoCs ace power management and functional safety in SoCs
- Analog and Power Management Trends in ASIC and SoC Designs
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow